The present invention relates to a semiconductor memory cell having at least two transistors merged into one unit or at least two transistors and a diode merged into one unit. Otherwise, the present invention relates to a semiconductor memory cell having two transistors and a junction-field-effect transistor merged into one unit or at least two transistors, a junction-field-effect transistor and a diode merged into one unit.
As a high-density semiconductor memory cell, conventionally, there is used a dynamic semiconductor memory cell that is called a single-transistor semiconductor memory cell including one transistor and one capacitor as shown in FIG. 67A. In the above semiconductor memory cell, an electric charge stored in the capacitor is required to be large enough to generate a sufficiently large voltage change on a bit line. However, with a decrease in the planar dimensions of the semiconductor memory cell, the capacitor formed in a parallel planar shape decreases in size, which causes the following new problem. When information stored as an electric charge in the capacitor of the semiconductor memory cell is read out, the read-out information is buried in a noise. Or, since the stray capacitance of the bit line in the semiconductor memory cell increases from generation to generation, only a small voltage change is generated on the bit line. As means for solving the above problems, there has been proposed a dynamic semiconductor memory cell having a trench capacitor cell structure as shown in FIG. 67B or a stacked capacitor cell structure. Since, however, the fabrication-related technology has its own limits on the depth of the trench (or groove) or the height of the stack, the capacitance of the capacitor is also limited. For this reason, dynamic semiconductor memory cells having the above structures are said to encounter the above limits unless expensive new materials are introduced for the capacitor as far as the dimensions thereof beyond the deep sub-micron rule (low sub-micron rule) are concerned.
In the planar dimensions smaller than those of the deep sub-micron rule (low sub-micron rule), the transistor constituting the semiconductor memory cell also has problems of deterioration of the drain breakdown voltage and a punchthrough from a drain region to a source region. There is therefore a large risk that current leakage takes place even if the voltage applied to the semiconductor memory cell is still within a predetermined range. When a semiconductor memory cell is made smaller in size, therefore, it is difficult to normally operate the semiconductor memory cell having a conventional transistor structure.
For overcoming the above limit problems of the capacitor, the present Applicant has proposed a semiconductor memory cell comprising two transistors or two transistors physically merged into one unit, as is disclosed in Japanese Patent Application No. 246264/1993 (JP-A-7-99251) corresponding to U.S. Pat. No. 5,428,238. The following explanation is made by referring to Japanese Patent Application No. 246264/1993 (JP-A-7-99251). The semiconductor memory cell shown in FIGS. 15(A) and 15(B) of the above Japanese Patent Application comprises a first semi-conductive region SC1 of a first conductivity type formed in a surface region of a semiconductor substrate or formed on an insulating substrate, a first conductive region SC2 formed in a surface region of the first semi-conductive region SC1 so as to form a rectifier junction together with the first semi-conductive region SC1, a second semi-conductive region SC3 of a second conductivity type formed in a surface region of the first semi-conductive region SC1 and spaced from the first conductive region SC2, a second conductive region SC4 formed in a surface region of the second semi-conductive region SC3 so as to form a rectifier junction together with the second semi-conductive region SC3, and a conductive gate G formed on a barrier layer so as to bridge the first semi-conductive region SC1 and the second conductive region SC4 and so as to bridge the first conductive region SC2 and the second semi-conductive region SC3, the conductive gate G being connected to a first memory-cell-selecting line, the first conductive region SC2 being connected to a write-in information setting line, and the second conductive region SC4 being connected to a second memory-cell-selecting line.
The first semi-conductive region SC1 (functioning as a channel forming region Ch2), the first conductive region SC2 and the second semi-conductive region SC3 (functioning as source/drain regions) and the conductive gate G constitute a switching transistor TR2. On the other hand, the second semi-conductive region SC3 (functioning as a channel forming region Ch1), the first semi-conductive region SC1 and the second conductive region SC4 (functioning as source/drain regions) and the conductive gate G constitute an information storing transistor TR1.
When information is written in the above semiconductor memory cell, the switching transistor TR2 is brought into an ON-state. As a result, the information is stored in the channel forming region Ch1 of the information storing transistor TR1 as a potential or as an electric charge. When the information is read out, the threshold voltage of the information storing transistor TR1 seen from the conductive gate G varies, depending upon the potential or the electric charge stored in the channel forming region Ch1 of the information storing transistor TR1. Therefore, when the information is read out, the storage state of the information storing transistor TR1 can be judged from the magnitude of a channel current (including a zero magnitude) by applying a properly selected potential to the conductive gate G. The information is read out by detecting the operation state of the information storing transistor TR1.
That is, when information is read out, the information storing transistor TR1 is brought into an ON-state or an OFF-state, depending upon the information stored therein. Since the second conductive region SC4 is connected to the second line, a current which is large or small depending upon the stored information (xe2x80x9c0 xe2x80x9d or xe2x80x9c1xe2x80x9d) flows in the information storing transistor TR1. In this way, the information stored in the semiconductor memory cell can be read out through the information storing transistor TR1.
Further, the present Applicant in Japanese Patent Application No. 251646/1997 (JP-A-10-154757) has proposed a semiconductor memory cell comprising three transistors such as a transistor TR1 for readout, a transistor TR2 for switching and a junction type transistor TR3 for current control.
In the semiconductor memory cells disclosed in the above Laid-open publications, however, the layout and structure of the regions are asymmetric with regard to a conductive gate, so that there is involved a problem that it is constantly required to advert to the direction of the conductive gate during designing and production of the semiconductor memory cells.
It is a first object of the present invention to provide a semiconductor memory cell, or a semiconductor memory cell for a logic, which permits a high freedom during designing or production thereof, which attains stabilized performances of a transistor, which requires no large capacitor unlike any conventional DRAM, which secures reliable writing and readout of information and which permits minimizing of dimensions, and further to a semiconductor memory cell in which at least two transistors, or at least two transistors and a diode are merged into one unit.
It is a second object of the present invention to provide a semiconductor memory cell, or a semiconductor memory cell for a logic, which permits a high freedom during designing or production thereof, which attains stabilized performances of a transistor, which requires no large capacitor unlike any conventional DRAM, which secures reliable writing and readout of information and which permits minimizing of dimensions, and further to a semiconductor memory cell in which at least two transistors and a junction-field-effect transistor, or at least two transistors, a junction-field-effect transistor and a diode are merged into one unit.
According to a first aspect of the present invention for achieving the above first object, there is provided a semiconductor memory cell comprising;
(1) a first transistor for readout, having source/drain regions, a channel forming region and a gate region and having a first conductivity type, and
(2) a second transistor for switching, having source/drain regions, a channel forming region and a gate region and having a second conductivity type,
the semiconductor memory cell having;
(a) a semi-conductive first region having a second conductivity type,
(b) a semi-conductive second region which is formed in a surface region of the first region and has a first conductivity type,
(c) a third region which is formed in a surface region of the second region and is in contact with the second region so as to form a rectifier junction together with the second region,
(d) a semi-conductive fourth region which is formed in a surface region of the first region and spaced from the second region and which has the first conductivity type,
(e) a fifth region which is formed in a surface region of the fourth region and is in contact together with the fourth region so as to form a rectifier junction together with the fourth region, and
(f) a gate region which is formed on an insulation layer so as to bridge the first region and the third region and so as to bridge the second region and the fourth region, and is shared by the first and second transistors,
wherein:
(A-1) one source/drain region of the first transistor is formed of a surface region of the second region,
(A-2) the other source/drain region of the first transistor is formed of a surface region of the fourth region,
(A-3) the channel forming region of the first transistor is formed of a surface region of the first region which surface region is interposed between said surface region of the second region and said surface region of the fourth region,
(B-1) one source/drain region of the second transistor is formed of said surface region of the first region which surface region forms the channel forming region of the first transistor,
(B-2) the other source/drain region of the second transistor is formed of the third region,
(B-3) the channel forming region of the second transistor is formed of said surface region of the second region which surface region forms the one source/drain region of the first transistor,
(C) the gate region is connected to a first line for memory cell selection,
(D) the third region is connected to a write-in information setting line,
(E) the fourth region is connected to a second line, and
(F) the fifth region is connected to the first region,
and further wherein:
when the semiconductor memory cell is cut with a first imaginary perpendicular plane which is perpendicular to the extending direction of the gate region and passes through the center of the gate region, the second region and the fourth region in the vicinity of the gate region are nearly symmetrical with respect to a second imaginary perpendicular plane which is in parallel with the extending direction of the gate region and passes through the center of the gate region.
In the present invention, the term xe2x80x9cimaginary perpendicular planexe2x80x9d refers to an imaginary plane perpendicular to the surface of the first region. Further, the term xe2x80x9cnearly symmetricalxe2x80x9d is used for including a concept that cases where xe2x80x9csymmetryxe2x80x9d varies depending upon methods of forming each region are included in cases where two regions are symmetrical. The term xe2x80x9cnearly symmetricalxe2x80x9d is also used in this sense hereinafter.
According to a second aspect of the present invention for achieving the above first object, there is provided a semiconductor memory cell comprising;
(1) a first transistor for readout, having source/drain regions, a channel forming region and a gate region and having a first conductivity type,
(2) a second transistor for switching, having source/drain regions, a channel forming region and a gate region and having a second conductivity type, and
(3) a third transistor for current control, having source/drain regions, a channel forming region and a gate region and having the second conductivity type,
the semiconductor memory cell having;
(a) a semi-conductive first region having a second conductivity type,
(b) a semi-conductive second region which is formed in a surface region of the first region and has a first conductivity type,
(c) a third region which is formed in a surface region of the second region and is in contact with the second region so as to form a rectifier junction together with the second region,
(d) a semi-conductive fourth region which is formed in a surface region of the first region and spaced from the second region and which has the first conductivity type,
(e) a fifth region which is formed in a surface region of the fourth region and is in contact together with the fourth region so as to form a rectifier junction together with the fourth region, and
(f) a gate region which is formed on an insulation layer so as to bridge the first region and the third region, so as to bridge the second region and the fourth region and so as to bridge the first region and fifth region, and is shared by the first, second and third transistors,
wherein:
(A-1) one source/drain region of the first transistor is formed of a surface region of the second region,
(A-2) the other source/drain region of the first transistor is formed of a surface region of the fourth region,
(A-3) the channel forming region of the first transistor is formed of a surface region of the first region which surface region is interposed between said surface region of the second region and said surface region of the fourth region,
(B-1) one source/drain region of the second transistor is formed of said surface region of the first region which surface region forms the channel forming region of the first transistor,
(B-2) the other source/drain region of the second transistor is formed of the third region,
(B-3) the channel forming region of the second transistor is formed of said surface region of the second region which surface region forms the one source/drain region of the first transistor,
(C-1) one source/drain region of the third transistor is formed of said surface region of the first region,
(C-2) the other source/drain region of the third transistor is formed of the fifth region,
(C-3) the channel forming region of the third transistor is formed of said surface region of the fourth region,
(D) the gate region is connected to a first line for memory cell selection,
(E) the third region is connected to a write-in information setting line, and
(F) the fourth region is connected to a second line,
and further wherein:
when the semiconductor memory cell is cut with a first imaginary perpendicular plane which is perpendicular to the extending direction of the gate region and passes through the center of the gate region, the second region and the fourth region in the vicinity of the gate region are nearly symmetrical with respect to a second imaginary perpendicular plane which is in parallel with the extending direction of the gate region and passes through the center of the gate region.
Further, in the semiconductor memory cell according to the first or second aspect of the present invention, preferably, the third region and the fifth region in the vicinity of the gate region are nearly symmetrical with respect of the above second imaginary perpendicular plane when the semiconductor memory cell is cut with the above first imaginary perpendicular plane.
In the semiconductor memory cell according to the first or second aspect of the present invention, it is preferred to employ a constitution in which the second region is connected to a third line, the second line is used as a bit line and a predetermined potential is applied to the third line, or a constitution in which the second region is connected to a third line, the third line is used as a bit line and a predetermined potential is applied to the second line.
Alternatively, in the semiconductor memory cell according to the first or second aspect of the present invention, for simplification of a wiring structure, it is preferred to employ a constitution in which a diode is formed of the second region and the third region, and the second region is connected to the write-in information setting line through the third region. In this case, it is preferred to employ a constitution in which the second line is used as a bit line or a constitution in which the write-in information setting line is used as a bit line as well and a predetermined potential is applied to the second line.
According to a third aspect of the present invention for achieving the above second object, there is provided a semiconductor memory cell comprising;
(1) a first transistor for readout, having source/drain regions, a channel forming region and a gate region and having a first conductivity type,
(2) a second transistor for switching, having source/drain regions, a channel forming region and a gate region and having a second conductivity type, and
(3) a junction-field-effect transistor for current control, having source/drain regions, a channel region and gate portions,
the semiconductor memory cell having;
(a) a semi-conductive first region having a second conductivity type,
(b) a semi-conductive second region which is formed in a surface region of the first region and has a first conductivity type,
(c) a third region which is formed in a surface region of the second region and is in contact with the second region so as to form a rectifier junction together with the second region,
(d) a semi-conductive fourth region which is formed in a surface region of the first region and spaced from the second region and which has the first conductivity type,
(e) a fifth region which is formed in a surface region of the fourth region and is in contact with the fourth region so as to form a rectifier junction together with the fourth region, and
(f) a gate region which is formed on an insulation layer so as to bridge the first region and the third region and so as to bridge the second region and the fourth region and is shared by the first and second transistors,
wherein:
(A-1) one source/drain region of the first transistor is formed of a surface region of the second region,
(A-2) the other source/drain region of the first transistor is formed of a surface region of the fourth region,
(A-3) the channel forming region of the first transistor is formed of a surface region of the first region which surface region is interposed between said surface region of the second region and said surface region of the fourth region,
(B-1) one source/drain region of the second transistor is formed of said surface region of the first region which surface region forms the channel forming region of the first transistor,
(B-2) the other source/drain region of the second transistor is formed of the third region,
(B-3) the channel forming region of the second transistor is formed of said surface region of the second region which surface region forms the one source/drain region of the first transistor,
(C-1) the gate portions of the junction-field-effect transistor are formed of the fifth region and a portion of the first region which portion is opposed to the fifth region,
(C-2) the channel region of the junction-field-effect transistor is formed of a portion of the fourth region which portion is interposed between the fifth region and said portion of the first region,
(C-3) one source/drain region of the junction-field-effect transistor is formed of said surface region of the fourth region which surface region extends from one end of the channel region of the junction-field-effect transistor and forms the other source/drain region of the first transistor,
(C-4) the other source/drain region of the junction-field-effect transistor is formed of a portion of the fourth region which portion extends from the other end of the channel region of the junction-field-effect transistor,
(D) the gate region is connected to a first line for memory cell selection,
(E) the third region is connected to a write-in information setting line,
(F) the fourth region is connected to a second line, and
(G) the fifth region is connected to a third line,
and further wherein:
when the semiconductor memory cell is cut with a first imaginary perpendicular plane which is perpendicular to the extending direction of the gate region and passes through the center of the gate region, the second region and the fourth region in the vicinity of the gate region is nearly symmetrical with respect to a second imaginary perpendicular plane which is in parallel with the extending direction of the gate region and passes through the center of the gate region.
In the semiconductor memory cell according to the third aspect of the present invention, there may be employed a constitution in which the fifth region is connected to the write-in information setting line in place of being connected to the third line, or a constitution in which the fifth region is connected to the first region in place of being connected to the third line.
In the semiconductor memory cell according to the third aspect of the present invention, there may be employed a constitution in which the semiconductor memory cell further comprises a second junction-field-effect transistor for current control, having source/drain regions, a channel region and gate portions,
the gate portions of the second junction-field-effect transistor are formed of the third region and a portion of the first region which portion is opposed to the third region,
the channel region of the second junction-field-effect transistor is formed of a portion of the second region which portion is interposed between the third region and said portion of the first region,
one source/drain region of the second junction-field-effect transistor is formed of said surface region of the second region which surface region extends from one end of the channel region of the second junction-field-effect transistor and forms the one source/drain region of the first transistor, and
the other source/drain region of the second junction-field-effect transistor is formed of a portion of the second region which portion extends from the other end of the channel region of the second junction-field-effect transistor.
In the above case, there may be employed a constitution in which the fifth region is connected to the first region in place of being connected to the third line.
A semiconductor memory cell according to the fourth aspect of the present invention for achieving the above second object further has a third transistor for current control, and in this point, it differs from the semiconductor memory cell according to the third aspect of the present invention. That is, the semiconductor memory cell according to the fourth aspect of the present invention comprises;
(1) a first transistor for readout, having source/drain regions, a channel forming region and a gate region and having a first conductivity type,
(2) a second transistor for switching, having source/drain regions, a channel forming region and a gate region and having a second conductivity type,
(3) a third transistor for current control, having source/drain regions, a channel forming region and a gate region and having the second conductivity type, and
(4) a junction-field-effect transistor for current control, having source/drain regions, a channel region and gate portions,
the semiconductor memory cell having;
(a) a semi-conductive first region having a second conductivity type,
(b) a semi-conductive second region which is formed in a surface region of the first region and has a first conductivity type,
(c) a third region which is formed in a surface region of the second region and is in contact with the second region so as to form a rectifier junction together with the second region,
(d) a semi-conductive fourth region which is formed in a surface region of the first region and spaced from the second region and which has the first conductivity type,
(e) a fifth region which is formed in a surface region of the fourth region and is in contact with the fourth region so as to form a rectifier junction together with the fourth region, and
(f) a gate region which is formed on an insulation layer so as to bridge the first region and the third region, so as to bridge the second region and the fourth region and so as to bridge the first region and the fifth region and is shared by the first, second and third transistors,
wherein:
(A-1) one source/drain region of the first transistor is formed of a surface region of the second region,
(A-2) the other source/drain region of the first transistor is formed of a surface region of the fourth region,
(A-3) the channel forming region of the first transistor is formed of a surface region of the first region which surface region is interposed between said surface region of the second region and said surface region of the fourth region,
(B-1) one source/drain region of the second transistor is formed of said surface region of the first region which surface region forms the channel forming region of the first transistor,
(B-2) the other source/drain region of the second transistor is formed of the third region,
(B-3) the channel forming region of the second transistor is formed of said surface region of the second region which surface region forms the one source/drain region of the first transistor,
(C-1) one source/drain region of the third transistor is formed of said surface region of the first region,
(C-2) the other source/drain region of the third transistor is formed of the fifth region,
(C-3) the channel forming region of the third transistor is formed of said surface region of the fourth region,
(D-1) the gate portions of the junction-field-effect transistor are formed of the fifth region and a portion of the first region which portion is opposed to the fifth region,
(D-2) the channel region of the junction-field-effect transistor is formed of a portion of the fourth region which portion is interposed between the fifth region and said portion of the first region,
(D-3) one source/drain region of the junction-field-effect transistor is formed of said surface region of the fourth region which surface region extends from one end of the channel region of the junction-field-effect transistor, forms the other source/drain region of the first transistor and forms the channel forming region of the third transistor,
(D-4) the other source/drain region of the junction-field-effect transistor is formed of a portion of the fourth region which portion extends from the other end of the channel region of the junction-field-effect transistor,
(E) the gate region is connected to a first line for memory cell selection,
(F) the third region is connected to a write-in information setting line, and
(G) the fourth region is connected to a second line, and
and further wherein:
when the semiconductor memory cell is cut with a first imaginary perpendicular plane which is perpendicular to the extending direction-of the gate region and passes through the center of the gate region, the second region and the fourth region in the vicinity of the gate region is nearly symmetrical with respect to a second imaginary perpendicular plane which is in parallel with the extending direction of the gate region and passes through the center of the gate region.
In the semiconductor memory cell according to the fourth aspect of the present invention, there may be employed a constitution in which the semiconductor memory cell further comprises a second junction-field-effect transistor for current control, having source/drain regions, a channel region and gate portions,
the gate portions of the second junction-field-effect transistor are formed of the third region and a portion of the first region which portion is opposed to the third region,
the channel region of the second junction-field-effect transistor is formed of a portion of the second region which portion is interposed between the third region and said portion of the first region,
one source/drain region of the second junction-field-effect transistor is formed of said surface region of the second region which surface region extends from one end of the channel region of the second junction-field-effect transistor and forms the one source/drain region of the first transistor, and
the other source/drain region of the second junction-field-effect transistor is formed of a portion of the second region which portion extends from the other end of the channel region of the second junction-field-effect transistor.
A semiconductor memory cell according to a fifth aspect of the present invention for achieving the above second object differs from the semiconductor memory cell according to the third aspect of the present invention in a position where the junction-field-effect transistor is formed. That is, the semiconductor memory cell according to the fifth aspect of the present invention comprises;
(1) a first transistor for readout, having source/drain regions, a channel forming region and a gate region and having a first conductivity type,
(2) a second transistor for switching, having source/drain regions, a channel forming region and a gate region and having a second conductivity type, and
(3) a junction-field-effect transistor for current control, having source/drain regions, a channel region and gate portions,
the semiconductor memory cell having;
(a) a semi-conductive first region having a second conductivity type,
(b) a semi-conductive second region which is formed in a surface region of the first region and has a first conductivity type,
(c) a third region which is formed in a surface region of the second region and is in contact with the second region so as to form a rectifier junction together with the second region,
(d) a semi-conductive fourth region which is formed in a surface region of the first region and spaced from the second region and which has the first conductivity type,
(e) a fifth region which is formed in a surface region of the fourth region and is in contact with the fourth region so as to form a rectifier junction together with the fourth region, and
(f) a gate region which is formed on an insulation layer so as to bridge the first region and the third region and so as to bridge the second region and the fourth region and is shared by the first and second transistors,
wherein:
(A-1) one source/drain region of the first transistor is formed of a surface region of the second region,
(A-2) the other source/drain region of the first transistor is formed of a surface region of the fourth region,
(A-3) the channel forming region of the first transistor is formed of a surface region of the first region which surface region is interposed between said surface region of the second region and said surface region of the fourth region,
(B-1) one source/drain region of the second transistor is formed of said surface region of the first region which surface region forms the channel forming region of the first transistor,
(B-2) the other source/drain region of the second transistor is formed of the third region,
(B-3) the channel forming region of the second transistor is formed of said surface region of the second region which surface region forms the one source/drain region of the first transistor,
(C-1) the gate portions of the junction-field-effect transistor are formed of the third region and a portion of the first region which portion is opposed to the third region,
(C-2) the channel region of the junction-field-effect transistor is formed of a portion of the second region which portion is interposed between the third region and said portion of the first region,
(C-3) one source/drain region of the junction-field-effect transistor is formed of said surface region of the second region which surface region extends from one end of the channel region of the junction-field-effect transistor and forms the one source/drain region of the first transistor,
(C-4) the other source/drain region of the junction-field-effect transistor is formed of a portion of the second region which portion extends from the other end of the channel region of the junction-field-effect transistor,
(D) the gate region is connected to a first line for memory cell selection,
(E) the third region is connected to a write-in information setting line,
(F) the fourth region is connected to a second line, and
(G) the fifth region is connected to the first region,
and further wherein:
when the semiconductor memory cell is cut with a first imaginary perpendicular plane which is perpendicular to the extending direction of the gate region and passes through the center of the gate region, the second region and the fourth region in the vicinity of the gate region are symmetrical with respect to a second imaginary perpendicular plane which is in parallel with the extending direction of the gate region and passes through the center of the gate region.
Differing from the semiconductor according to the third aspect of the present invention, the fifth region does not take part in the constitution of the junction-field-effect transistor. Since, however, the fifth region and the first region are connected to each other, a region where information is to be stored can be increased, and the length of time period for which the semiconductor memory cell stores information can be increased.
The junction-field-effect transistor (JFET) or the second junction-field-effect transistor in the semiconductor memory cell according to each of the third to fifth aspects of the present invention can be formed by
(i) optimizing the distance between the opposing gate portions of each junction-field-effect transistor (thickness of the channel region), and
(ii) optimizing the impurity concentration of the opposing gate portions of each junction-field-effect transistor and the impurity concentration of the channel region of each junction-field-effect transistor.
When the distance between the gate portions (thickness of the channel region) and the impurity concentration of each of the gate portions and the channel region are not optimized, a depletion layer does not broaden, and no ON-OFF operation of each junction-field-effect transistor can be obtained. The above optimization is required to be attained by computer simulation or experiments.
Further, in the semiconductor memory cell according to the third, fourth or fifth aspect of the present invention, preferably, when semiconductor memory cell is cut with the above first imaginary perpendicular plane, the third region and the fifth region in the vicinity of the gate region are nearly symmetrical with respect to the above second imaginary perpendicular plane.
In the semiconductor memory cell according to the third aspect of the present invention, it is preferred to employ a constitution in which the second region is connected to a fourth line, the second line is used as a bit line and a predetermined potential is applied to the fourth line, or a constitution in which the second region is connected to a fourth line, the fourth line is used as a bit line and a predetermined potential is applied to the second line.
In the semiconductor memory cell according to the fourth or fifth aspect of the present invention, it is preferred to employ a constitution in which the second region is connected to a third line, the second line is used as a bit line and the a predetermined potential is applied to the third line, or a constitution in which the second region is connected to a third line, the third line is used as a bit line and a predetermined potential is applied to the second line.
Alternatively, in the semiconductor memory cell according to the third, fourth or fifth aspect of the present invention including various variants, for simplification of a wiring structure, it is preferred to employ a constitution in which a diode is formed of the second region and the third region, and the second region is connected to the write-in information setting line through the third region. In this case, it is preferred to employ a constitution in which the second line is used as a bit line, or a constitution in which the write-in information setting line is used as a bit line as well and a predetermined potential is applied to the second line.
When the third region is formed of a semi-conductive region having an opposite conductivity type to the second region, the diode is a pn junction diode, and the pn junction diode can be formed by adjusting impurity concentrations of these regions forming the pn junction diode to proper values. When potentials in the regions forming the pn junction diode are set improperly, or when designing of the relationship of the impurity concentrations in these regions is improper, carriers injected from the above pn junction diode may latch up the semiconductor memory cell.
For avoiding the above failure, it is preferred to employ a constitution in which a diode-constituting region is formed in a surface region of the second region to be in contact with the second region so as to form a rectifier junction together with the second region, a majority carrier diode is formed of the diode-constituting region and the second region, and the second region is connected to the write-in information setting line through the diode-constituting region. The diode-constituting region is preferably made from a material which forms a Schottky junction or an ISO type hetero-junction in which such a diode operates on the basis of majority carriers in the second region and majority carriers are not injected even when a forward-direction bias is applied to the junction portion. That is, the rectifier junction is preferably a majority carrier junction such as a Schottky junction or an ISO type hetero-junction. The term xe2x80x9cISO type hetero-junctionxe2x80x9d refers to a hetero-junction formed between two semi-conductive regions which have an identical conductivity type but are different in kind. Particulars of the ISO type hetero-junction are described in xe2x80x9cPhysics of Semiconductor Devicesxe2x80x9d, S. M. Sze, 2nd Edition, page 122 (issued by John Wiley and Sons). In the above Schottky junction or ISO type hetero-junction, the forward-direction voltage is lower than the forward-direction voltage in a pn junction. The majority carrier diode having the above properties can avoid the latch-up phenomenon. The Schottky junction can be formed when the diode-constituting region is made of a metal such as aluminum, molybdenum or titanium or silicide such as TiSi2 or WSi2. The ISO type hetero-junction can be formed when the diode-constituting region is made of a semi-conductive material which differs from a material constituting the second region and which has the same conductivity type as the conductivity type of the second region. The diode-constituting region may be made of the same material as a material (for example, titanium silicide or TiN for use as a barrier layer or a glue layer) used for constituting the write-in information setting line. That is, there can be employed a structure in which the diode-constituting region is formed in a surface region of the second region and the so-formed diode-constituting region is used as part of the write-in information setting line. The above structure in which xe2x80x9cthe diode-constituting region is used as part of the write-in information setting linexe2x80x9d also includes a state where the diode-constituting region is made of a compound formed by a reaction between a wiring material and silicon of a silicon semiconductor substrate.
In the semiconductor memory cell according to the second aspect of the present invention, preferably, an impurity-containing layer having the second conductivity type is formed in a surface region of the fourth region forming the channel forming region of the third transistor. In this case, when information is retained, and when the potential of the first line is set at 0 volt, the third transistor is brought into an ON-state, and the fifth region and the first region are brought into a conduction sate. Preferably, the impurity content of the impurity-containing layer is adjusted such that the third transistor is brought into an OFF-state by a potential which is applied to the first line when information is read out.
The semiconductor memory cell of the present invention may be formed in a surface region of a semiconductor substrate, on an insulating layer formed on a semiconductor substrate, in a well structure formed in a semiconductor substrate or on an insulator. For coping with a soft-error caused by a particle or neutron, preferably, the semiconductor memory cell is formed in a well structure or on an insulator (insulating layer), or it has a so-called SOI structure or a TFT structure. The insulator or insulating layer may be formed not only on a semiconductor substrate, but also on a glass substrate or a quartz substrate.
In the semiconductor memory cell of the present invention, it is preferred to form a high-impurity-concentration layer having a first conductivity type below the first region, since, in this case, the potential or charge stored in the channel forming region of the first transistor can be increased.
The channel forming region can be made from silicon, GaAs or the like according to a conventional method. The gate region of the first transistor or the second transistor can be made from a metal, an impurity-containing silicon, an impurity-containing amorphous silicon, an impurity-containing polysilicon, silicide, or GaAs containing a high concentration of an impurity, according to a conventional method. The insulation layer can be made from SiO2, Si3N4, Al2O3 or GaAlAs according to a conventional method. Each region can be made from an impurity-containing silicon, an impurity-containing amorphous silicon, an impurity-containing polysilicon, silicide, silicon-germanium (Sixe2x80x94Ge) or GaAs containing a high concentration of an impurity according to a conventional method depending upon required properties and structure thereof.
In the semiconductor memory cell of the present invention, the third region may be made from silicide, a metal or a metal compound depending upon required properties. However, the third region is preferably made from a semiconductor. Further, the fifth region may be made from a semiconductor, or it may be made from silicide, a metal or a metal compound.
In the present invention, when the semiconductor memory cell is cut with the first imaginary perpendicular plane, the second and fourth regions in the vicinity of the gate region are symmetrical with respect to the second imaginary perpendicular plane, and in some constitutions, further, the third and fifth regions in the vicinity of the gate region are symmetrical with respect to the second imaginary perpendicular plane. Therefore, the freedom during designing or production of the semiconductor memory cell can be increased.
In the semiconductor memory cell of the present invention, further, the gate region is common to the first transistor and the second transistor and is connected to the first line for memory cell selection, so that one line is sufficient for the first line for memory cell selection, which serves to decrease a chip area. Further, since the first transistor for readout and the second transistor for switching are merged into one unit, so that a cell area can be decreased and that a leak current can be decreased.
In the semiconductor memory cell of the present invention, the ON-OFF state of the first transistor and the second transistor can be controlled by selecting a proper potential in the first line for memory cell selection. That is, when information is written in, the potential of the first line for memory cell section is set at a level at which the second transistor is sufficiently turned on. Therefore, the second transistor is brought into conduction, and a charge is stored in a capacitor formed between the channel forming region and one source/drain region of the second transistor depending upon a potential of the write-in information setting line. As a result, information is stored in the channel forming region of the first transistor in the form of a potential difference between the channel forming region of the second transistor and the channel forming region of the first transistor, or a charge. When the information is read out, the potential of the source/drain region of the first transistor comes to be a readout potential, and in the first transistor, the potential or charge (information) stored in the channel forming region is converted to a potential difference between the channel forming region and the other source/drain region or a charge, and the threshold value of the first transistor, seen from the gate region, changes depending upon the above charge (information). When information is read out, a properly selected potential is applied to the gate region, whereby the ON-OFF operation of the first transistor can be controlled. The operation state of the first transistor is detected, whereby the information can be read out.
Further, a diode obviates the third line which is to be connected to one source/drain region (second region) of the first transistor. In the above semiconductor memory cell of the present invention, when the potentials are improperly set in the regions constituting the diode, or when the impurity concentration relationship of these regions is designed improperly, a latch-up phenomenon may take place during writing of information if the voltage applied to the write-in information setting line is not at a low level (for example, smaller than, or equal to, 0.4 volt when the junction is a pn junction) at which no large forward-direction current flows in the junction portion of the third region and the second region. For avoiding the latch-up phenomenon, there is provided a method as is already explained, in which a diode-constituting region is formed in a surface region of the second region, and the diode-constituting region is made of a silicide, a metal or a metal compound, to form a Schottky junction or an ISO type hetero-junction as a junction of the diode-constituting region and the second region, so that majority carriers mainly constitute a forward-direction current.
In the semiconductor memory cell according to any one of the third to fifth aspects of the present invention, further, the junction-field-effect transistor is provided in addition to the first transistor of a first conductivity type and the second transistor of a second conductivity type. The ON-OFF operation of the junction-field-effect transistor is controlled when the information is read out, so that a margin of a current which flows between the source/drain regions of the first transistor can be remarkably broadened. As a result, there is almost no limitation to be imposed on the number of the semiconductor memory cells that can be connected, for example, to the second line. Further, when the third transistor for current control is provided, the ON-OFF operation is controlled during reading of information, so that a margin of a current which flows between the source/drain regions of the first transistor can be more reliably remarkably broadened. As a result, the number of the semiconductor memory cells that can be connected, for example, to the second line is limited to a far less degree.
The semiconductor memory cell of the present invention retains information in the form of a potential, a potential difference or a charge, while it is attenuated by a lead current such as junction leak and a refreshing operation is required. The semiconductor memory cell therefore operates like DRAM.